CS42432-DMZ datasheet(28/59 Pages) CIRRUS

28 / 59 page

DS673F1

CS42432

Running the CS42432 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

Disabling the high-pass filter and freezing the stored DC offset.

5.2.2.1

Hardware Mode

The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode.

5.2.2.2

Software Mode

The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high-pass filters are controlled us-

ing the HPF_FREEZE bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 42.

5.3

Analog Outputs

5.3.1

Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 10 on page 29. The CS42432

enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma

modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog

and analog-to-digital converters and switched-capacitor low-pass filters are powered down.

The device remains in the power-down state until the RST pin is brought high. The control port is acces-

sible once RST is high, and the desired register settings can be loaded per the interface descriptions in

the “Control Port Description and Timing” on page 33. In Hardware Mode operation, the Hardware Mode

pins must be set up before RST is brought high. All features will default to the Hardware Mode defaults

as listed in Table 2.

Once MCLK is valid, VQ will quickly charge to VA/2, and the internal voltage reference, FILT+, will begin

powering up to normal operation. Power is applied to the D/A converters and switched-capacitor filters, and

the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are

counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000

sample period delay, normal operation begins.

5.3.2

Line-Level Outputs and Filtering

The CS42432 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin-

gle-ended outputs on AOUT1-AOUT

6. These amplifiers are biased to a quiescent DC level of approxi-

mately VQ.

The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of

which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using

an off-chip low-pass filter.

See “DAC Output Filter” on page 50 for recommended output filter. The active filter configuration accounts

for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a

passive filter configuration which minimizes costs and the number of components.

Figure 11 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately

VA/2.

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