CS8420-CSZ datasheet(59/94 Pages) CIRRUS

59 / 94 page

DS245F4

CS8420

13.3

Hardware Mode 2 Description

(DEFAULT Data Flow, Serial Input)

Hardware Mode 2 data flow is shown in Figure 25. Audio data is input via the serial audio input port, and

rate converted. The audio data at the new rate is then output both via the serial audio output port and via

the AES3 transmitter.

The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin.

When CUVEN is low, mode 2A is selected, where COPY/C, ORIG/U, and EMPH/V pins allow selected

channel status data bits to be set. The COPY and ORIG pins are used to set the pro bit, the copy bit, and

the L bit, as shown in Table 9. In consumer mode, the transmitted category code shall be 0101100b, which

indicates sample rate converter. The transmitted U and V bits are zero.When the CUVEN pin is high, mode

2B is selected, where COPY/C, ORIG/U, and EMPH/V become serial bit inputs for C, U, and V data. This

data is clocked by both edges of OLRCK, and the channel status block start is indicated or determined by

TCBL. Figure 20 shows the timing requirements.

Audio serial port data formats are selected as shown in Tables 6, 7 and 10.

Start-up options are shown in Table 11, and allow choice of the serial audio output port as a master or slave

and whether TCBL is an input or an output. The serial audio input port is always a slave.

AES3

Encoder

&Tx

Serial

Audio

Output

Serial

Audio

Input

Sample

Rate

Converter

C&Ubit Data Buffer

Clocked by

Output Clock

Clocked by

Input Derived Clock

ILRCK

ISCLK

OLRCK

OSCLK

SDOUT

TXP

TXN

RMCK

LOCK

COPY/C ORIG/U EMPH/V CUVEN TCBL

DFC0

DFC1

S/AES

VD+

H/S

Output

Clock

Source

OMCK

Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)

areomittedfromthis diagram. Please refer to the Typical Connection Diagram for hook-up details.

VD+

SDIN

SFMT1 SFMT0

Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input

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