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CS5343 датащи(PDF) 10 Page - Cirrus Logic

номер детали CS5343
подробное описание детали  98 dB, 96 kHz, Multi-Bit Audio A/D Converter
PDF  21 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5343 датащи(HTML) 10 Page - Cirrus Logic

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DS687F1
CS5343/4
SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE
Logic “0” = GND = 0 V; Logic “1” = VA, CL = 20 pF.
Parameter
Symbol
Min
Typ
Max
Unit
Master Mode
MCLK Period
(Double-Speed, 384x Mode)
tclkw
24
-
30
ns
(Double-Speed, 192x Mode)
48
-
60
ns
(Double-Speed, 256x Mode)
36
-
45
ns
(Double-Speed, 128x Mode)
72
-
90
ns
(Single-Speed, 768x Mode)
24
-
325
ns
(Single-Speed, 384x Mode)
48
-
651
ns
(Single-Speed, 512x Mode)
36
-
488
ns
(Single-Speed, 256x Mode)
72
-
976
ns
MCLK Duty Cycle
40
50
60
%
Output Sample Rate
(Single-Speed)
(Double-Speed)
Fs
4
86
-
-
54
108
kHz
kHz
LRCK Duty Cycle
-
50
-
%
SCLK Duty Cycle
-
50
-
%
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
40
-
-
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
Slave Mode
MCLK Period
(Double-Speed, 384x Mode)
tclkw
24
-
30
ns
(Double-Speed, 192x Mode)
48
-
60
ns
(Double-Speed, 256x Mode)
36
-
45
ns
(Double-Speed, 128x Mode)
72
-
90
ns
(Single-Speed, 768x Mode)
24
-
325
ns
(Single-Speed, 384x Mode)
48
-
651
ns
(Single-Speed, 512x Mode)
36
-
488
ns
(Single-Speed, 256x Mode)
72
-
976
ns
MCLK Duty Cycle
40
50
60
%
Input Sample Rate
(Single-Speed)
(Double-Speed)
Fs
4
86
-
-
54
108
kHz
kHz
LRCK Duty Cycle
405060
%
SCLK Period
tsclkw
--
ns
SCLK Duty Cycle
455055
%
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
40
-
-
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
1
64
Fs
×
------------------



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