26

DS658F2

CS5345

4.7

Control Port Description and Timing

The control port is used to access the registers, allowing the CS5345 to be configured for the desired oper-

ational modes and formats. The operation of the control port may be completely asynchronous with respect

to the audio sample rates. However, to avoid potential interference problems, the control port pins should

remain static if no operation is required.

The control port has two modes: SPI and I²C, with the CS5345 acting as a slave device. SPI Mode is se-

lected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C

Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently

selecting the desired AD0 bit address state.

4.7.1

SPI Mode

In SPI Mode, CS is the CS5345 chip-select signal; CCLK is the control port bit clock (input into the CS5345

from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data

line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 10 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The

first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-

cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data that will

be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z

state. It may be externally pulled high or low with a 47 k

Ω resistor, if desired.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which

finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-

dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the

addressed register (CDOUT will leave the high-impedance state).

For both read and write cycles, the memory address pointer will automatically increment following each

data byte in order to facilitate block reads and writes of successive registers.

4.7.2

I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should

MA P

MSB

LSB

DATA

by te 1

by te n

R/W

R/W

AD D R ES S

CH IP

ADDRESS

CHIP

CD IN

CC L K

CS

CD OU T

MSB

LSB MSB

LSB

1001111

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 10. Control Port Timing in SPI Mode