10

DS608F1

CS5342

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT

10. For a description of speed modes, please refer to Table 1 on page 14

11. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.

Parameter

Symbol

Min

Typ

Max

Unit

MCLK Specifications

MCLK Period

26

-

30

ns

52

-

1302

ns

MCLK Pulse Duty Cycle

40

-

60

%

Master Mode

SCLK falling to LRCK

-20

-

20

ns

SCLK falling to SDOUT valid

--

32

ns

SCLK Duty Cycle

Single-Speed

Double-Speed

Quad-Speed

-

-

-

50

50

33

-

-

-

%

%

%

Slave Mode

Single-Speed (Note 10)

LRCK Duty Cycle

40

-

60

%

SCLK Period

313

-

-

ns

SCLK Duty Cycle

45

-

55

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-20

-

20

ns

Double-Speed (Note 10)

LRCK Duty Cycle

40

-

60

%

SCLK Period (Note 11)

208

-

-

ns

SCLK Duty Cycle

45

-

55

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-20

-

20

ns

Quad-Speed (Note 10)

LRCK Duty Cycle

40

-

60

%

SCLK Period (Note 11)

104

-

-

ns

SCLK Duty Cycle

40

-

50

%

SDOUT valid before SCLK rising

10

-

-

ns

SDOUT valid after SCLK rising

5-

-

ns

SCLK falling to LRCK edge

-8

-

8

ns