DS786A1

13

CS4412A

4. APPLICATIONS

4.1

Overview

The CS4412A is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as

four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or

one parallel full-bridge channel.

The CS4412A integrates on-chip over-current, under-voltage, over-temperature protection and error report-

delivering 85% efficiency. This efficiency provides for smaller device package, no external heat sink require-

ments, and smaller power supplies.

4.2

Reset and Power-Up

Reliable power-up can be accomplished by keeping the device in reset until the power supplies and config-

uration pins are stable. It is also recommended that the RST12 and RST34 pins be activated if the voltage

supplies drop below the recommended operating condition to prevent power-glitch related issues.

When the RST12 or RST34 are low, the corresponding channels of the CS4412A enter a low-power mode;

all of the channels’ internal states are reset and the corresponding power output pins are held in a high-

impedance state. When RST12 or RST34 are high, the corresponding outputs will begin normal operation

according to the RAMP, CNFG[2:0], and IN1 - IN4 pins.

4.2.1

PWM Popguard Transient Control

The CS4412A uses PWM Popguard technology to minimize the effects of output transients during power-

up and power-down for half-bridge configurations. This technique reduces the audio transients commonly

produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set high, the corre-

sponding power outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time

for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up tran-

sient. The corresponding outputs will not begin normal operation until the ramp has reached the bias point.

The time it takes to complete a ramp-up sequence will vary slightly from the applied VP voltage; typical

ramp-up speeds achieved with a 1000

μF DC blocking capacitor are listed in Table 2. These times will

scale with the value of the capacitor.

VP Voltage

Typical Ramp Time*

12 V

1.25 seconds

15 V

0.95 seconds

18 V

0.80 seconds

* With 1000

μF DC Blocking Capacitor.

Table 2. Typical Ramp Times for Typical VP Voltages