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PACE1750A

Document # MICRO-3 Rev. C

Notes

1. 4.5V

2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in

parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced.

When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high

impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.

Min

Max

Min

Max

Min

Max

Min

Max

45

30

25

20

ns

SNEW

45

30

26

22

ns

TRIGO RST

45

30

26

22

ns

45

40

35

30

ns

DMA enable

45

40

35

30

ns

Normal power up

45

40

35

30

ns

Clock to major error unrecoverable

75

60

50

45

ns

RESET

65

50

40

30

ns

Console request

0000

ns

Console request

10

10

10

10

ns

Level sensitive faults

5555

ns

Level sensitive faults

5555

ns

0000

ns

Power down interrupt level sensitive

hold

10

10

10

10

ns

30

25

20

15

ns

Clock to three-state

30

22

17

13

ns

Edge sensitiive pulse width

5555

ns

Clock rise and fall

55

55

ns

40 MHz

Unit

SIGNAL PROPAGATION DELAYS

Symbol

Parameter

20 MHz

30 MHz

15 Mhz