DSPIC30F3012AT20ESLASHML datasheet(115/205 Pages) MICROCHIP

115 / 205 page

DS70139E-page 113

dsPIC30F2011/2012/3012/3013

The configuration procedures below give the required

setup values for the conversion speeds above 100

ksps.

16.7.1

200 KSPS CONFIGURATION

GUIDELINE

The following configuration items are required to

achieve a 200 ksps conversion rate.

• Comply with conditions provided in Table 16-1.

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 16-2.

• Set SSRC<2.0> = 111 in the ADCON1 register to

enable the auto convert option.

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register.

• Write the SMPI<3.0> control bits in the ADCON2

between interrupts.

• Configure the ADC clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register.

• Configure the sampling time to be 1 TAD by

writing: SAMC<4:0> = 00001.

The following figure shows the timing diagram of the

ADC running at 200 ksps. The TAD selection in conjunc-

tion with the guidelines described above allows a con-

version speed of 200 ksps. See Example 16-1 for code

example.

16.8

A/D Acquisition Requirements

The analog input model of the 12-bit ADC is shown in

Figure 16-3. The total sampling time for the A/D is a

function of the internal amplifier settling time and the

holding capacitor charge time.

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the voltage level on the analog input pin. The

source impedance (RS), the interconnect impedance

(RIC), and the internal sampling switch (RSS) imped-

ance combine to directly affect the time required to

charge the capacitor CHOLD. The combined imped-

ance of the analog sources must therefore be small

enough to fully charge the holding capacitor within the

chosen sample time. To minimize the effects of pin

leakage currents on the accuracy of the ADC, the max-

imum recommended source impedance, RS, is 2.5 k

Ω.

After the analog input channel is selected (changed),

this sampling function must be completed prior to start-

ing the conversion. The internal holding capacitor will

be in a discharged state prior to each sample opera-

tion.

FIGURE 16-3:

12-BIT A/D CONVERTER ANALOG INPUT MODEL

(14 + 1) x 200,000

= 334 ns

CPIN

ANx

VT = 0.6V

I leakage

RIC

≤ 250Ω

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

VDD

= 18 pF

± 500 nA

Legend: CPIN

I leakage

RIC

RSS

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch resistance

= sample/hold capacitance (from DAC)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs

≤ 2.5 kΩ.

RSS

≤ 3 kΩ

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