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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F258-E/LSQTP датащи(PDF) 116 Page - Microchip Technology |
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PIC18F258-E/LSQTP датащи(HTML) 116 Page - Microchip Technology |
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116 / 402 page  PIC18FXX8 DS41159E-page 114 © 2006 Microchip Technology Inc. 12.1 Timer1 Operation Timer1 can operate in one of these modes: •As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON register). When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section 15.1 “CCP1 Module”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE TMR1H TMR1L T1SYNC TMR1CS T1CKPS1:T1CKPS0 Sleep Input FOSC/4 Internal Clock TMR1ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 TMR1IF Overflow TMR1 CLR CCP Special Event Trigger T1OSCEN Enable Oscillator(1) T1OSC Interrupt Flag bit Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. T1OSI T1CKI/T1OSO Timer 1 TMR1L T1OSC T1SYNC TMR1CS T1CKPS1:T1CKPS0 Sleep Input T1OSCEN Enable Oscillator(1) TMR1IF Overflow Interrupt FOSC/4 Internal Clock TMR1ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 T1CKI/T1OSO T1OSI TMR1 Flag bit Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. High Byte Data Bus<7:0> 8 TMR1H 8 8 8 Read TMR1L Write TMR1L Special Event Trigger |
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