PIC18F23K20-ESLASHSP datasheet(37/420 Pages) MICROCHIP

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Advance Information

DS41303B-page 35

PIC18F2XK20/4XK20

2.9

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS<1:0>) bits of the

OSCCON register.

2.9.1

SYSTEM CLOCK SELECT

(SCS<1:0>) BITS

The System Clock Select (SCS<1:0>) bits of the OSC-

CON register select the system clock source that is

used for the CPU and peripherals.

• When SCS<1:0> = 00, the system clock source is

determined by configuration of the FOSC<2:0>

bits in the CONFIG1H Configuration register.

• When SCS<1:0> = 10, the system clock source is

chosen by the internal oscillator frequency

selected by the INTSRC bit of the OSCTUNE

• When SCS<1:0> = 01, the system clock source is

the 32.768 kHz secondary oscillator shared with

Timer1.

After a Reset, the SCS<1:0> bits of the OSCCON

2.9.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<3:0> bits in the CONFIG1H

Configuration register, or from the internal clock

source. In particular, when the primary oscillator is the

source of the primary clock, OSTS indicates that the

Oscillator Start-up Timer (OST) has timed out for LP,

XT or HS modes.

2.10

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the HFINTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

When the Oscillator module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 2.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

execution switches to the external oscillator.

2.10.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is enabled when all of the

following settings are configured as noted:

• Two-Speed Start-up mode is enabled by setting

the IESO of the CONFIG1H Configuration register

is set. Fail-Safe mode (FCMEM=1) also enables

two-speed by default.

• SCS<1:0> (of the OSCCON register) = 00.

• FOSC<2:0> bits of the CONFIG1H Configuration

Two-Speed Start-up mode becomes active after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then Two-

Speed Start-up is disabled. This is because the external

clock oscillator does not require any stabilization time

after POR or an exit from Sleep.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe

Clock

Monitor,

does

not

update

the

SCS<1:0> bits of the OSCCON register.

The user can monitor the T1RUN bit of the

T1CON register and the IOFS and OSTS

bits of the OSCCON register to determine

the current system clock source.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

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