PIC18F23K20-ESLASHSOSQTP datasheet(117/420 Pages) MICROCHIP

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Advance Information

DS41303B-page 115

PIC18F2XK20/4XK20

9.9

INTn Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxF, is set. This interrupt can be disabled by

clearing the corresponding enable bit, INTxE. Flag bit,

INTxF, must be cleared by software in the Interrupt

Service Routine before re-enabling the interrupt.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from Idle or Sleep modes if bit INTxE

was set prior to going into those modes. If the Global

Interrupt Enable bit, GIE, is set, the processor will

branch to the interrupt vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP and

INT2IP of the INTCON3 register. There is no priority bit

associated with INT0. It is always a high priority inter-

rupt source.

9.10

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh

→ 00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh

→ 0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TMR0IE of the INTCON register. Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TMR0IP of the INTCON2 register.

See Section 11.0 “Timer0 Module” for further details

on the Timer0 module.

9.11

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF of

the INTCON register. The interrupt can be enabled/

disabled by setting/clearing enable bit, RBIE of the

INTCON register. Pins must also be individually

enabled with the IOCB register. Interrupt priority for

PORTB interrupt-on-change is determined by the value

contained in the interrupt priority bit, RBIP of the

INTCON2 register.

9.12

Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 9-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR, BSR_TEMP

; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP, BSR

; Restore BSR

MOVF

W_TEMP, W

; Restore WREG

MOVFF

STATUS_TEMP, STATUS

; Restore STATUS

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