PIC18F23K20-ESLASHSOSQTP datasheet(95/420 Pages) MICROCHIP

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Advance Information

DS41303B-page 93

PIC18F2XK20/4XK20

6.5

Writing to Flash Program Memory

The programming block size is 8, 32 or 64 bytes,

depending on the device (See Table 6-1). Word or byte

programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are only as many holding registers as there are bytes

in a write block (See Table 6-1).

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction may need to be executed 8, 32,

or 64 times, depending on the device, for each pro-

gramming operation. All of the table write operations

will essentially be short writes because only the holding

registers are written. After all the holding registers have

been written, the programming operation of that block

of memory is started by configuring the EECON1 regis-

ter for a program memory write and performing the long

write sequence.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted during a long

write cycle. The long write will be terminated by the

internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 6-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

6.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

Read 64 bytes into RAM.

Update data values in RAM as necessary.

Load Table Pointer register with address being

erased.

Execute the block erase procedure.

Load Table Pointer register with address of first

byte being written.

Write the 8, 32 or 64 byte block into the holding

registers with auto-increment.

Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

Disable interrupts.

Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

13. Re-enable interrupts.

14. Repeat steps 6 to 13 for each block until all 64

bytes are written.

15. Verify the memory (table read).

This procedure will require about 6 ms to update each

write block of memory. An example of the required code

is given in Example 6-3.

Note:

The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modify that byte. This means that

individual bytes of program memory may be

modified, provided that the change does not

attempt to change any bit from a ‘0’ to a ‘1’.

When modifying individual bytes, it is not

necessary to load all holding registers

before executing a long write operation.

TABLAT

TBLPTR = xxxxYY

(1)

TBLPTR = xxxx01

TBLPTR = xxxx00

Write Register

TBLPTR = xxxx02

Program Memory

Holding Register

Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the bytes in the

holding registers.

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