PIC16F690 datasheet(62/294 Pages) MICROCHIP

62 / 294 page

PIC16F631/677/685/687/689/690

DS41262D-page 60

4.2

Additional Pin Functions

Every PORTA pin on this device family has an

interrupt-on-change option and a weak pull-up option.

RA0 also has an Ultra Low-Power Wake-up option. The

next three sections describe these functions.

4.2.1

ANSEL AND ANSELH REGISTERS

The ANSEL and ANSELH registers are used to disable

the input buffers of I/O pins, which allow analog voltages

to be applied to those pins without causing excessive

current. Setting the ANSx bit of a corresponding pin will

cause all digital reads of that pin to return ‘0’ and also

permit analog functions of that pin to operate correctly.

The state of the ANSx bit has no effect on the digital

output function of its corresponding pin. A pin with the

TRISx bit clear and ANSx bit set will operate as a digital

output, together with the analog input function of that

pin. Pins with the ANSx bit set always read ‘0’, which

can cause unexpected behavior when executing read

write

operations

the

port

due

the

read-modify-write sequence of all such operations.

4.2.2

WEAK PULL-UPS

Each of the PORTA pins, except RA3, has an

individually configurable internal weak pull-up. Control

bits WPUAx enable or disable each pull-up. Refer to

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RABPU bit of the OPTION register. A weak pull-up is

automatically enabled for RA3 when configured as

MCLR and disabled when RA3 is an I/O. There is no

software control of the MCLR pull-up.

4.2.3

INTERRUPT-ON-CHANGE

Each PORTA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCAx enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTA Change Interrupt Flag

bit (RABIF) in the INTCON register (Register 2-6).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

Any read or write of PORTA. This will end the

mismatch condition, then,

Clear the flag bit RABIF.

A mismatch condition will continue to set flag bit RABIF.

Reading PORTA will end the mismatch condition and

allow flag bit RABIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOR

Reset. After these Resets, the RABIF flag will continue

to be set if a mismatch is present.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RABIF

interrupt flag may not get set.

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