PIC16F688-ESLASHMLQTP datasheet(19/202 Pages) MICROCHIP

19 / 202 page

DS41203D-page 17

PIC16F688

2.2.2.5

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE bit of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0

R-0

R/W-0

R-0

R/W-0

EEIF

ADIF

RCIF

C2IF

C1IF

OSFIF

TXIF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EEIF: EEPROM Write Operation Interrupt Flag bit

= The write operation completed (must be cleared in software)

= The write operation has not completed or has not been started

bit 6

ADIF: A/D Converter Interrupt Flag bit

= A/D conversion complete (must be cleared in software)

= A/D conversion has not completed or has not been started

bit 5

RCIF: EUSART Receive Interrupt Flag bit

= The EUSART receive buffer is full (cleared by reading RCREG)

= The EUSART receive buffer is not full

bit 4

C2IF: Comparator C2 Interrupt Flag bit

= Comparator output (C2OUT bit) has changed (must be cleared in software)

= Comparator output (C2OUT bit) has not changed

bit 3

C1IF: Comparator C1 Interrupt Flag bit

= Comparator output (C1OUT bit) has changed (must be cleared in software)

= Comparator output (C1OUT bit) has not changed

bit 2

OSFIF: Oscillator Fail Interrupt Flag bit

= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

= System clock operating

bit 1

TXIF: EUSART Transmit Interrupt Flag bit

= The EUSART transmit buffer is empty (cleared by writing to TXREG)

= The EUSART transmit buffer is full

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

= The TMR1 register overflowed (must be cleared in software)

= The TMR1 register did not overflow

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