(Preliminary)

1.8V-3.3V PicoTreo

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/07 Page 2

2

3

4

5

6

7

8

9

CLK4/CSEL^

VDD

CLK3

XOUT

CLK0

VDD

CLK2/OEM^/PDB^

MSOP-10L

10

1

GND

XIN/FIN

CLK1

PIN CONFIGURATION

^ Denotes internal pull up

PACKAGE PIN ASSIGNMENT

Package Pin #

Name

MSOP-10L

SOP-8L

Type

Description

GND

1

5

P

GND connection

CLK4/CSEL

2

-

B*

- Programmable Clock (CLK4) output or

- Configuration Switching input

CLK2/OEM/PDB

3

2

B*

- Programmable Clock (CLK2) output, or

- Output Enable Master (OEM) for all clock outputs, or

- Power Down mode (PDB) input

VDD

4, 8

3, 7

P

VDD connection

CLK3

5

-

O

Programmable Clock (CLK3) output

CLK0

6

4

B*

Programmable Clock (CLK0) output

CLK1

7

6

O

Programmable Clock (CLK1) output

XOUT

9

8

O

Crystal output pin. Do Not Connect when using FIN

XIN/FIN

10

1

I

Crystal or Reference Clock input

* Note:

All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In

configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.

KEY PROGRAMMING PARAMETERS

CLK[ 0:4 ]

Output Frequency

Output Drive Strength

Programmable Input/Output

CLK[0]

CLK[1,2]

CLK[3]

CLK[4]

M = 11 bit

R = 8 bit

P = 5 bit (Odd/Even Divider)

Each output has

three optional drive

strengths to choose

from. They are:

 Low: 4mA

 Std: 8mA (default)

 High:16mA

Most pins are multi-function I/Os and can be

configured as:

 OEM – (Master OE controlling all outputs)

 CSEL – (Device Configuration Switching)

 PDB – (Power Down)



CLK[0:4] – (Output)



HiZ or Active Low disabled state

1

2

3

4

5

6

7

8

XIN/FIN

VDD

CLK0

XOUT

CLK1

GND

VDD

CLK2/OEM^/PDB^

SOP-8L