C8051F062 datasheet(39/328 Pages) SILABS

39 / 328 page

C8051F060/1/2/3/4/5/6/7

Rev. 1.2

Pinout and Package Definitions

Table 4.1. Pin Definitions

Name

Pin Numbers

Type Description

F060

F061

F064

F065

F062

F063

F066

F067

VDD

37, 64,

26, 40,

37, 64,

26, 40,

Digital Supply Voltage. Must be tied to +2.7 to

+3.6 V.

DGND

38, 63,

27, 39,

38, 63,

27, 39,

Digital Ground. Must be tied to Ground.

AV+

11, 16,

7, 10,

11, 16,

7, 10,

Analog Supply Voltage. Must be tied to +2.7 to

+3.6 V.

AVDD

Analog Supply Voltage. Must be tied to +2.7 to

+3.6 V.

AGND

10, 14,

17, 23

6, 11,

19, 22

10, 14,

17, 23

6, 11,

19, 22

Analog Ground. Must be tied to Ground.

TMS

D In

JTAG Test Mode Select with internal pull-up.

TCK

D In

JTAG Test Clock with internal pull-up.

TDI

D In

JTAG Test Data Input with internal pull-up. TDI is

latched on the rising edge of TCK.

TDO

D Out JTAG Test Data Output with internal pull-up. Data is

shifted out on TDO on the falling edge of TCK. TDO

output is a tri-state driver.

/RST

100

D I/O Device Reset. Open-drain output of internal VDD

monitor. Is driven low when VDD is <2.7 V and

MONEN is high. An external source can initiate a

system reset by driving this pin low.

XTAL1

A In

Crystal Input. This pin is the return for the internal

oscillator circuit for a crystal or ceramic resonator.

For a precision internal clock, connect a crystal or

ceramic resonator from XTAL1 to XTAL2. If over-

driven by an external CMOS clock, this becomes

the system clock.

XTAL2

A Out Crystal Output. This pin is the excitation driver for a

crystal or ceramic resonator.

MONEN

D In

VDD Monitor Enable. When tied high, this pin

enables the internal VDD monitor, which forces a

system reset when VDD is < 2.7 V. When tied low,

the internal VDD monitor is disabled. Recom-

mended configuration is to connect directly to VDD.

VREF

A Out Bandgap Voltage Reference Output

VREF0

A I/O Bandgap Voltage Reference Output for ADC0.

ADC0 Voltage Reference Input.

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