PIC18F4321 datasheet(40/396 Pages) MICROCHIP

40 / 396 page

PIC18F4321 FAMILY

DS39689E-page 38

Preliminary

3.4.1

PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm-up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC3:FOSC0 Configuration bits. The OSTS

bit remains set (see Figure 3-7).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD (parame-

ter 38, Table 26-10) is required between the wake event

and when code execution starts. This is required to

allow the CPU to become ready to execute instructions.

After the wake-up, the OSTS bit remains set. The

IDLEN and SCS bits are not affected by the wake-up

(see Figure 3-8).

3.4.2

SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by

setting the IDLEN bit and executing a SLEEP

instruction. If the device is in another Run mode, set the

IDLEN bit first, then set the SCS1:SCS0 bits to ‘01’ and

execute SLEEP. When the clock source is switched to

the Timer1 oscillator, the primary oscillator is shut down,

the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-8).

FIGURE 3-7:

TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8:

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note:

The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when writing

the SCS<1:0> bits, entry to SEC_IDLE

mode will not occur. If the Timer1 oscillator

is enabled but not yet running, peripheral

clocks will be delayed until the oscillator

has started. In such situations, initial oscil-

lator operation is far from stable and

unpredictable operation may result.

Peripheral

Program

PC + 2

OSC1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program

CPU Clock

Clock

Counter

Wake Event

TCSD

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