June 1994

9

Philips Semiconductors

Product specification

8-bit high-speed analog-to-digital converter

TDF8704

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must be less than 1 ns.

3. Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.

4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The

calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).

Conversion to signal-to-noise ratio: S/N = EB

× 6.02 + 1.76 dB.

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two

input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

7. Measurement taken using video analyser VM700A.

sampling delay time

−−

2ns

output hold time

5

−−

ns

output delay time

−

12

15

ns

3-state output delay times (see Figs 6 and 7)

enable HIGH

−

610

ns

enable LOW

−

12

16

ns

disable HIGH

−

50

54

ns

disable LOW

−

10

14

ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fig.3

5 V supply.

handbook, halfpage

60

3.49

3.43

3.45

3.47

MBD868

1.29

1.23

1.25

1.27

V I (T)

(V)

VI (B)

(V)

20

20

60

100

T

( C)

o

0.1 mV/K

0.05 mV/K

VI (T)

VI (B)

amb

Fig.4

andbook, halfpage

4.25

4.75

5.75

3.44

3.38

3.40

3.42

MSA689

5.25

1.28

1.22

1.24

1.26

V I (T)

(V)

V I (B)

(V)

17 mV/V

7 mV/V

V

(V)

CC

VI (T)

V I (B)