Data Sheet

AD8016

Rev. C | Page 5 of 20

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

Rating

Supply Voltage

26.4 V

Internal Power Dissipation

SOIC_W_BAT Package1

1.4 W

TSSOP_EP Package2

1.4 W

Input Voltage (Common-Mode)

±VS

Differential Input Voltage

±VS

Output Short-Circuit Duration

Observe power derating

curves

Storage Temperature Range

−65°C to +125°C

Operating Temperature Range

−40°C to +85°C

Lead Temperature Range (Soldering 10 sec)

300°C

1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper

at 85°C 24-lead SOIC_W_BAT package: θJA = 28°C/W.

2 Specification is for device on a 4-layer board with 9 inches2 of 1 oz copper at

85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the

AD8016 is limited by the associated rise in junction temper-

ature. The maximum safe junction temperature for a plastic

encapsulated device is determined by the glass transition

temperature of the plastic, approximately 150°C. Temporarily

exceeding this limit may cause a shift in parametric perfor-

mance due to a change in the stresses exerted on the die by

the package.

The output stage of the AD8016 is designed for maximum load

current capability. As a result, shorting the output to common

can cause the AD8016 to source or sink 2000 mA. To ensure

proper operation, it is necessary to observe the maximum

power derating curves. Direct connection of the output to

either power supply rail can destroy the device.

Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for

TJ = 125 °C

ESD CAUTION

AMBIENT TEMPERATURE (°C)

7

6

5

4

3

2

1

0

010

SOIC_W_BAT

8

TSSOP-EP

20

30

40

50

60

70

80

90