M62023L datasheet(7/13 Pages) RENESAS

7 / 13 page

M62023L/P/FP

REJ03D0528-0200 Rev.2.00 Jun 15, 2007

Page 7 of 12

Timing Chart

tpd

VSH

VSL

VOL(

CS)

VOL(RES)

VOL(

RES)

VOH(

RES)

V1=VIN-VDROP

V2=VIN-VEB(SW Tr.)

V3=VBAT-VF

VIN

VOUT

RES

VIN(VSL)

∆Vs

Input voltage

In normal operation

In failure

(instantaneous drop)

Restoration from failure

(instantaneous drop)

In backup state

Output

Input voltage: 3V

→2V

Each output varies if the input

voltage drops to VSL or under

Input voltage: 2V

→3V

If the input voltage goes higher

than VSL by 100mV, each output

varies after delay produced by

the delay circuit.

Input voltage: 0V

Backup voltage: 3V

VOUT

With SW Tr. set to ON, a

voltage (VIN-VDROP) is output.

SW Tr. is turned OFF. A voltage

(VIN-VEB) is output by the diode

between E and B of SW Tr.

SW Tr. is turned ON after delay

and a voltage (VIN-VDROP) is

output.

VBAT-VF

RES

The output level is

VOL (RES) with a logic low.

As the state shifts from a logic low

to logic high, the output level

becomes approximately equal to

the input voltage.

A logic high is maintained, and

then shifts to a logic low.

RES

The output level is VOH(RES)

with a logic high.

As the state shifts from a logic

high to logic low, the output level

becomes VOL(RES)

A logic low is maintained, and

then shifts to a logic high.

The output level is VOL(CS)

with a logic low.

As the state shifts from a logic low

to logic high, the output level

becomes the voltage VIN-VEB.

A logic high is maintained, and

then shifts to a logic low.

The output is a logic

high and the output

level is VBAT-VF

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