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M30302FAPFP датащи(PDF) 31 Page - Renesas Technology Corp |
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M30302FAPFP датащи(HTML) 31 Page - Renesas Technology Corp |
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31 / 57 page ![]() M16C/30P Group 5. Electrical Characteristics Rev.1.22 Mar 30, 2007 Page 31 of 53 REJ03B0088-0122 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. The condition is VCC1=VCC2=3.0 to 5.0V. NOTES: 1. Calculated according to the BCLK frequency as follows: 2. Calculated according to the BCLK frequency as follows: n is ”2” for 1-wait setting. Table 5.11 External Clock Input (XIN input) (1) Symbol Parameter Standard Unit Min. Max. tc External Clock Input Cycle Time 62.5 ns tw(H) External Clock Input HIGH Pulse Width 25 ns tw(L) External Clock Input LOW Pulse Width 25 ns tr External Clock Rise Time 15 ns tf External Clock Fall Time 15 ns Table 5.12 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard Unit Min. Max. tac1(RD-DB) Data Input Access Time (for setting with no wait) (NOTE 1) ns tac2(RD-DB) Data Input Access Time (for setting with wait) (NOTE 2) ns tsu(DB-RD) Data Input Setup Time 40 ns tsu(RDY-BCLK) RDY Input Setup Time 30 ns tsu(HOLD-BCLK) HOLD Input Setup Time 40 ns th(RD-DB) Data Input Hold Time 0 ns th(BCLK-RDY) RDY Input Hold Time 0 ns th(BCLK-HOLD) HOLD Input Hold Time 0 ns 0.5x10 9 fBCLK () ------------------------45 ns [] – n0.5 – ()x10 9 fBCLK () -------------------------------------45 ns [] – |
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