TDA9321 datasheet(29/44 Pages) PHILIPS

29 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

HORIZONTAL OSCILLATOR

ffr

free-running frequency

−

15625

−

∆f

spread on free-running

frequency

−−

±2%

∆f/∆VP

frequency dependency with

respect to the supply voltage

VP = 8.0 V ±10%; note 6

−

0.2

0.5

∆f/T

frequency variation with

temperature

Tamb = 0 to 70 °C; note 6

−−

FIRST CONTROL LOOP (PIN PH1LF); note 33

fhr(PLL)

PLL holding range

−±0.9

±1.2

kHz

fcr(PLL)

PLL catching range

note 6

±0.6

±0.9

−

kHz

S/N

signal-to-noise ratio

for the video input signal

at which the time

constant is switched

hyssw

hysteresis at the switching point

σϕ

sigma value of phase jitter

in automatic mode;

±3 σ−

−

5ns

HORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT/OUTPUT (PIN HA/CLP)

Switched to HA output (bit HO = 1)

VOH

HIGH-level output voltage

Io(source) = 2 mA

4.0

5.0

5.5

VOL

LOW-level output voltage

Io(sink) = 2mA

−

0.2

0.4

Io(sink)

output sink current

−−

Io(source)

output source current

−−

pulse width

at nominal horizontal

frequency

4.6

4.7

4.8

µs

delay between mid sync of input

and mid HA pulse

note 30

0.3

0.45

0.6

µs

Switched to CLP output (bit HO = 0)

pulse width

at nominal horizontal

frequency

3.5

3.6

3.7

µs

td1

delay between start of CLP

pulse to start of black set-up

bit HD = 1 or

bit MACP = 1;

bits YD3 to YD0 = 1011;

at nominal horizontal

frequency

5.2

5.3

5.4

µs

td2

delay between mid sync of input

and start CLP pulse

note 30

3.0

3.2

3.4

µs

Switched to CLP input (bit ECL = 1)

VIL

LOW-level input voltage

−

0.6

VIH

HIGH-level input voltage

2.4

−

5.5

tW(clamp)

clamping pulse width

1.8

3.5

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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