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DSPIC33FJ12MC02ESS датащи(PDF) 201 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS датащи(HTML) 201 Page - Microchip Technology |
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201 / 284 page ![]() © 2007 Microchip Technology Inc. Preliminary DS70265B-page 199 dsPIC33FJ12MC201/202 19.0 10-BIT/12-BIT ANALOG-TO- DIGITAL CONVERTER (ADC) The dsPIC33FJ12MC201/202 devices have up to 6 ADC module input channels. The AD12B bit (ADxCON1<10>) allows each of the ADC modules to be configured as either a 10-bit, 4- sample-and-hold ADC (default configuration) or a 12- bit, 1 sample-and-hold ADC. 19.1 Key Features The 10-bit ADC configuration has the following key features: • Successive Approximation (SAR) conversion • Conversion speeds of up to 1.1 Msps • Up to 6 analog input pins • External voltage reference input pins • Simultaneous sampling of up to four analog input pins • Automatic Channel Scan mode • Selectable conversion trigger source • Selectable Buffer Fill modes • Four result alignment options (signed/unsigned, fractional/integer) • Operation during CPU Sleep and Idle modes • 16-word conversion result buffer The 12-bit ADC configuration supports all the above features, except: • In the 12-bit configuration, conversion speeds of up to 500 ksps are supported • There is only 1 sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. Depending on the particular device pinout, the ADC can have up to 6 analog input pins, designated AN0 through AN5. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs can be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. A block diagram of the ADC is shown in Figure 19-1. 19.2 ADC Initialization To configure the ADC module: 1. Select port pins as analog inputs (ADxPCFGH<15:0> or ADxPCFGL<15:0>). 2. Select voltage reference source to match expected range on analog inputs (ADxCON2<15:13>). 3. Select the analog conversion clock to match the desired data rate with the processor clock (ADxCON3<5:0>). 4. Determine how many sample-and-hold chan- nels will be used (ADxCON2<9:8> and ADxPCFGH<15:0> or ADxPCFGL<15:0>). 5. Select the appropriate sample/conversion sequence (ADxCON1<7:5> and ADxCON3<12:8>). 6. Select the way conversion results are presented in the buffer (ADxCON1<9:8>). 7. Turn on the ADC module (ADxCON1<15>). 8. Configure ADC interrupt (if required): a) Clear the ADxIF bit. b) Select the ADC interrupt priority. Note: This data sheet summarizes the features of the dsPIC33FJ12MC201/202 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters. Note: The ADC module must be disabled before the AD12B bit can be modified. |
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