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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDA9150 датащи(PDF) 21 Page - NXP Semiconductors |
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TDA9150 датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 36 page  July 1994 21 Philips Semiconductors Preliminary specification Programmable deflection controller TDA9150B CHARACTERISTICS VCC = 8V;Tamb = 25 °C; DGND = AGND = 0 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCC supply voltage 7.2 8.0 8.8 V ICC supply current note 1; fclk = 6.75 MHz − 27 − mA Ptot total power dissipation − 220 − mW Vpor power-on reset POR 1-to-0 transition − 6.25 7.0 V POR 0-to-1 transition 5.0 5.75 − V SDA and SCL (pins 17 and 18) V17 SDA input voltage 0 − 5.5 V VIL LOW level input voltage (pin 17) −− 1.5 V VIH HIGH level input voltage (pin 17) 3.5 −− V IIL LOW level input current (pin 17) V17 = VSSD −− −10 µA IIH HIGH level input current (pin 17) V17 = VCC −− 10 µA VOL LOW level output voltage (pin 17) IIL = 3 mA −− 0.4 V V18 SCL input voltage 0 − 5.5 V VIL LOW level input voltage (pin 18) −− 1.5 V VIH HIGH level input voltage (pin 18) 3.5 −− V IIL LOW level input current (pin 18) V18 = VSSD −− −10 µA IIH HIGH level input current (pin 18) V18 = VCC −− 10 µA Line-locked clock and line-locked clock select (pins 14 and 5) VIL LOW level input voltage (pin 14) −− 0.8 V VIH HIGH level input voltage (pin 14) 2.0 −− V I14 input current V14 = <5.5 V −10 − +10 µA tr rise time 0 − 1 ⁄2tLLC tf fall time 0 − 1 ⁄2tLLC δ0 duty factor LLCS = logic 0; at 1.4 V; note 2 40 50 60 % δ1 duty factor LLCS = logic 1; at 1.4 V; note 2 25 50 75 % TIMING (PRESCALER ON;fclk = 1⁄2fLLC WHERE fclk = INTERNAL CLOCK) fLLC line-locked clock frequency 12.4 − 29.2 MHz K line-locked clock frequency ratio between fLLC and fH H locked 856 864 865 H unlocked − 866 − line-locked clock frequency ratio between fclk and fH H locked 428 432 432.5 H unlocked − 433 − |
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