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TDA8784 датащи(PDF) 13 Page - NXP Semiconductors |
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TDA8784 датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 28 page ![]() 1999 Sep 21 13 Philips Semiconductors Product specification 18 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8784 Table 1 Serial interface programming Note 1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref. Vref is connected to ground via a capacitance. Table 2 Standby selection ADDRESS BITS DATA BITS D9 to D0 A2 A1 A0 0 0 0 OFD output control (D7 to D0). 0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0. 0 1 0 AGC gain control (D8 to D0). 0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and clock ADC: D0 = 1: CDS + AGC in standby; ICCA +ICCD =48mA D1 = 1: OFD DAC in standby; ICCA +ICCD =98mA D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA +ICCD = 98.5 mA D3 = 1: SHP and SHD activated with falling edge (for positive pulse) D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1 D5 = 0: CLKADC activated with falling edge D6 must be set to logic 0. 1 0 0 Clamp reference DAC (D9 to D0). STDBY DATA BITS D9 to D0 ICCA +ICCD (TYP.) 1LOW 4 mA 0 active 99 mA |
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