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CDCE949PW датащи(PDF) 22 Page - Texas Instruments

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номер детали CDCE949PW
подробное описание детали  Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs
PDF  31 Pages
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CDCE949PW датащи(HTML) 22 Page - Texas Instruments

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CDCE949
CDCEL949
SCAS844 – JUNE 2007
Table 12. PLL3 Configuration Register (continued)
OFFSET(1)
Bit(2)
Acronym
Default(3)
DESCRIPTION
38h
7:0
PLL3_0N [11:4
PLL3_0: 30-Bit Multiplier/Divider value for frequency fVCO3_0
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
39h
7:4
PLL3_0N [3:0]
3:0
PLL3_0R [8:5]
000h
3Ah
7:3
PLL3_0R[4:0]
2:0
PLL3_0Q [5:3]
10h
3Bh
7:5
PLL3_0Q [2:0]
4:2
PLL3_0P [2:0]
010b
fVCO3_0 range selection:
00 – fVCO3_0 < 125 MHz
01 – 125 MHz
≤ f
VCO3_0 < 150 MHz
1:0
VCO3_0_RANGE
00b
10 – 150 MHz
≤ f
VCO3_0 < 175 MHz
11 – fVCO3_0 ≥ 175 MHz
3Ch
7:0
PLL3_1N [11:4]
PLL3_1: 30-Bit Multiplier/Divider value for frequency fVCO3_1
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
3Dh
7:4
PLL3_1N [3:0]
3:0
PLL3_1R [8:5]
000h
3Eh
7:3
PLL3_1R[4:0]
2:0
PLL3_1Q [5:3]
10h
3Fh
7:5
PLL3_1Q [2:0]
4:2
PLL3_1P [2:0]
010b
fVCO3_1 range selection:
00 – fVCO3_1 < 125 MHz
01 – 125 MHz
≤ f
VCO3_1 < 150 MHz
1:0
VCO3_1_RANGE
00b
10 – 150 MHz
≤ f
VCO3_1 < 175 MHz
11 – fVCO3_1 ≥ 175 MHz
22
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