TDA8764HLSLASH8 datasheet(10/28 Pages) PHILIPS

10 / 28 page

1999 Jan 12

Philips Semiconductors

Preliminary speciﬁcation

10-bit high-speed low-power ADC with

internal reference regulator

TDA8764

Switching characteristics

CLOCK INPUT; CLK; see Fig.5; note 1

fclk(max)

maximum clock frequency

TDA8764TS/4; TDA8764HL/4

−−

MHz

TDA8764TS/8; TDA8764HL/8

−−

MHz

tCPH

clock pulse width HIGH

TDA8764TS/4; TDA8764HL/4

−−

TDA8764TS/8; TDA8764HL/8

−−

tCPL

clock pulse width LOW

TDA8764TS/4; TDA8764HL/4

−−

TDA8764TS/8; TDA8764HL/8

−−

Analog signal processing

LINEARITY

INL

integral non-linearity

TDA8764TS/4; TDA8764HL/4

fclk = 40 MHz; ramp input

−±0.8

tbf

LSB

TDA8764TS/8; TDA8764HL/8

fclk = 80 MHz; ramp input

−±0.8

tbf

LSB

DNL

differential non-linearity

TDA8764TS/4; TDA8764HL/4

fclk = 40 MHz; ramp input

−±0.25 tbf

LSB

TDA8764TS/8; TDA8764HL/8

fclk = 80 MHz; ramp input

−±0.25 tbf

LSB

Eoffset

offset error

middle code

−±1

−

LSB

gain error (from device to device)

using internal reference voltage

note 5

−

tbf

−

BANDWIDTH (fclk =40MHZ)/4 VERSION;

analog bandwidth

full-scale sine wave; note 6

−

MHz

75% full-scale sine wave;

note 6

−

MHz

small signal at mid-scale;

VI = ±10 LSB at code 512;

note 6

−

350

−

MHz

tstLH

analog input settling time

LOW-to-HIGH

full-scale square wave;

see Fig.7 and note 7

−

tbf

tstHL

analog input settling time

HIGH-to-LOW

full-scale square wave;

see Fig.7 and note 7

−

tbf

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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