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DS1821 датащи(PDF) 13 Page - Dallas Semiconductor

номер детали DS1821
подробное описание детали  Programmable Digital Thermostat and Thermometer
PDF  18 Pages
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производитель  DALLAS [Dallas Semiconductor]
домашняя страница  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1821 датащи(HTML) 13 Page - Dallas Semiconductor

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DS1821
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Figure 9 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15 μs for a read time slot.
Figure 10 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read time slots towards the end of the 15
μs period.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8
DETAILED MASTER READ 1 TIMING Figure 9
RECOMMENDED MASTER READ 1 TIMING Figure 10
VDD
GND
1-WIRE BUS
15
μs
VIH of Master
TRC
TINT > 1 μs
Master samples
VDD
GND
1-WIRE BUS
15
μs
VIH of Master
TRC =
small
TINT =
small
Master samples
LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)
Bus master pulling low
DS1821 pulling low
Resistor pullup
45
μs
15
μs
VDD
GND
1-WIRE BUS
60
μs < TX “0” < 120
1
μs < TREC <
∞
DS1821 samples
MIN
TYP
MAX
15
μs
30
μs
> 1
μs
MASTER WRITE “0” SLOT
MASTER WRITE “1” SLOT
DS1821 samples
MIN
TYP
MAX
VDD
GND
1-WIRE BUS
15
μs
MASTER READ “0” SLOT
MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1
μs
1
μs < TREC <
∞
15
μs
15
μs
30
μs
15
μs
> 1
μs



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