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TDA8764HL/4 датащи(PDF) 12 Page - NXP Semiconductors

номер детали TDA8764HL/4
подробное описание детали  10-bit high-speed low-power ADC with internal reference regulator
PDF  28 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8764HL/4 датащи(HTML) 12 Page - NXP Semiconductors

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1999 Jan 12
12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with
internal reference regulator
TDA8764
TWO-TONE; note 9
TTID
two-tone intermodulation distortion
fclk = 40 MHz
−
tbf
−
dB
fclk = 80 MHz
−
tbf
−
dB
BIT ERROR RATE
BER
bit error rate
fi = 5 MHz; Vi = ±16 LSB at
code 512
fclk = 40 MHz
−
10−13
−
times/
sample
fclk = 80 MHz
−
10−13
−
times/
sample
Timing (fclk = 40 MHz; CL = 10 pF) /4 version; see Fig.5 and note 10
tds
sampling delay time
−−
2ns
th
output hold time
5
−−
ns
td
output delay time
VCCO = 2.7 V
tbf
12
tbf
ns
VCCO = 3.3 V
tbf
11
tbf
ns
CL
digital output load capacitance
−−
10
pF
SR
slew rate
VCCO = 2.7 V; CL =10pF
−−
tbf
V/
µs
Timing (fclk = 80 MHz; CL = 10 pF) /8 version; see Fig.5 and note 10
tds
sampling delay time
−−
2ns
th
output hold time
4
−−
ns
td
output delay time
VCCO = 2.7 V
tbf
8
tbf
ns
VCCO = 3.3 V
tbf
7
tbf
ns
CL
digital output load capacitance
−−
10
pF
SR
slew rate
VCCO = 2.7 V; CL =10pF
−−
tbf
V/
µs
3-state output delay times (fclk = 40 MHz) /4 version; see Fig.6
tdZH
enable HIGH
−
tbf
tbf
ns
tdZL
enable LOW
−
tbf
tbf
ns
tdHZ
disable HIGH
−
tbf
tbf
ns
tdLZ
disable LOW
−
tbf
tbf
ns
3-state output delay times (fclk = 80 MHz) /8 version; see Fig.6
tdZH
enable HIGH
−
tbf
tbf
ns
tdZL
enable LOW
−
tbf
tbf
ns
tdHZ
disable HIGH
−
tbf
tbf
ns
tdLZ
disable LOW
−
tbf
tbf
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT



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