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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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24LC128-I/MS датащи(PDF) 7 Page - Microchip Technology |
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24LC128-I/MS датащи(HTML) 7 Page - Microchip Technology |
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7 / 42 page  © 2007 Microchip Technology Inc. DS21930B-page 7 24AAXX/24LCXX/24FCXX TABLE 2-3: AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02C All Parameters apply across all recommended operating ranges unless otherwise noted Industrial (I): TA = -40°C to +85°C, VCC = 1.7V to 5.5V Automotive (E): TA = -40°C to +125°C, VCC = 4.5V to 5.5V Parameter Symbol Min. Max. Units Conditions Clock frequency FCLK — — — 100 100 400 kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Clock high time THIGH 4000 4000 600 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Clock low time TLOW 4700 4700 1300 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V SDA and SCL rise time (Note 1) TR — — — 1000 1000 300 ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V SDA and SCL fall time TF — 300 ns (Note 1) Start condition hold time THD:STA 4000 4000 600 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Start condition setup time TSU:STA 4700 4700 600 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Data input hold time THD:DAT 0— ns (Note 2) Data input setup time TSU:DAT 250 250 100 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Stop condition setup time TSU:STO 4000 4000 600 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Output valid from clock (Note 2) TAA — — — 3500 3500 900 ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Bus free time: Time the bus must be free before a new transmis- sion can start TBUF 4700 4700 1300 — — — ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range) 1.7V ≤ Vcc ≤ 4.5V 4.5V ≤ Vcc ≤ 5.5V Output fall time from VIH minimum to VIL maximum TOF 20+0.1 CB 250 ns (Note 1), CB ≤ 100 pF Input filter spike suppression (SDA and SCL pins) TSP —50 ns (Note 1) Write cycle time TWC —4 1.5 ms 24XX00 24C01C, 24C02C Endurance 1,000,000 — cycles (Note 3) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com. |
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