TC1270AMVRCTR datasheet(22/40 Pages) MICROCHIP

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TC1270A/70AN/71A

DS22035B-page 22

4.5

Reset Generator Circuit

The output signals from the Voltage Detect Circuit and

the Manual Reset with Glitch Filter Circuit are OR’d

together and is used to activate the Reset Generator

Module.

After the reset conditions have been removed (the MR

pin is no longer forced low and the input voltage is

greater than the Trip Point voltage), the Reset Genera-

tor circuit determines the reset delay timeout required.

There are three options for the delay circuit. These are:

• 2.19 ms (typical) delay

• 35 ms (typical) delay

• 280 ms (typical) delay

4.5.1

RESET DELAY TIMER

The Reset delay timer ensures that the TC127XA

device will “hold” the embedded system in Reset until

the system voltage has stabilized. The Reset delay

timer time out is shown in Table 4-4.

The Reset Delay Timer starts once the Voltage

Detector Circuit output AND the Manual Reset with

Glitch Filter Circuit output become inactive. While the

Reset Delay Timer is active, the RST or RST pin is

driven to the active state. Once the Reset Delay Timer

times-out, the RST or RST pin is driven inactive.

The Reset delay timer (tRST) starts after the device

voltage rises above the “actual” trip point (VTRIP).

When the Reset delay timer times out, the Reset output

pin (RST/RST) is driven inactive.

The Reset Delay Timer is cleared, if either (or both) the

Voltage Detector Circuit output OR the Manual Reset

with Glitch Filter Circuit output become active. The RST

or RST pin continues to be driven to the active state.

Figure 4-12 illustrates when the Reset Delay Timer

(tRST) is active or inactive.

4.5.2

EFFECT OF TEMPERATURE ON

RESET POWER-UP TIMER (tRPU)

The Reset delay timer time out period (tRST)

determines how long the device remains in the Reset

condition. This time out is affected by both the device

VDD and temperature. Typical responses for different

VDD values and temperatures are shown in

Figures 2-28, 2-29 and 2-30.

TABLE 4-4:

RESET DELAY TIMER

TIME OUTS

FIGURE 4-12:

Reset Power-up Timer

Waveform.

tRST

Units

Min

Typ

Max

1.09

2.19

4.38

17.5

140

280

560

↑↑

This is the

minimum time that

the Reset Delay

Timer will “hold”

the Reset pin

active after VDD

rises above VTRIP

This is the

maximum time

that the Reset

Delay Timer will

“hold” the Reset

pin active after

VDD rises above

VTRIP

Note 1:

Shaded rows are custom ordered time

outs.

VTRIP

VDD

RST

tRST

Reset Delay

Timer Inactive

Reset

Delay

Timer

Inactive

See Figures 2-9,

2-7 and 2-8

See Figures 2-12, 2-11 and 2-10

See Figures 2-9,

2-7 and 2-8

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