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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP9805T-BE/ST датащи(PDF) 21 Page - Microchip Technology |
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MCP9805T-BE/ST датащи(HTML) 21 Page - Microchip Technology |
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21 / 34 page  © 2005 Microchip Technology Inc. DS21977B-page 21 MCP9805 FIGURE 5-1: Device Addressing. 5.1.5 DATA VALID After the Start condition, each bit of data in transmis- sion needs to be settled for a time specified by tSU-DATA before SCLK toggles from low-to-high (see Serial Interface Timing Characteristics). 5.1.6 ACKNOWLEDGE (ACK) Each receiving device, when addressed, is obliged to generate an ACK bit after the reception of each byte. The master device must generate an extra clock pulse for ACK to be recognized. The acknowledging device pulls down the SDA line for tSU-DATA before the low-to-high transition of SCLK from the master. SDA also needs to remain pulled down for tH-DATA after a high-to-low transition of SCLK. During read, the master must signal an End-of-Data (EOD) to the slave by not generating an ACK bit (NAK) once the last bit has been clocked out of the slave. In this case, the slave will leave the data line released to enable the master to generate the Stop condition. 5.1.7 TIME OUT If the SCLK stays high or low for a time specified by tOUT, the MCP9805 releases the bus and resets the serial interface. The master will have to restart the communication cycle with a Start condition. This dictates the minimum clock speed. 1 2345 67 8 9 SCLK SDA 0 0 1 1 A2 A1 A0 Start Address Byte Slave Address R/W MCP9805 Response Code Address A C K |
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