MCP3021 datasheet(15/26 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

DS21805A-page 15

MCP3021

5.0

SERIAL COMMUNICATIONS

5.1

I2C Bus Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (refer to Figure 5-1).

5.1.1

BUS NOT BUSY (A)

Both data and clock lines remain high.

5.1.2

START DATA TRANSFER (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a START condition. All

commands must be preceded by a START condition.

5.1.3

STOP DATA TRANSFER (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a STOP condition. All

operations must be ended with a STOP condition.

5.1.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

data bytes transferred between the START and STOP

conditions is determined by the master device and is

unlimited.

5.1.5

ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge bit after the reception of

each byte. The master device must generate an extra

clock pulse that is associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Setup

and hold times must be taken into account. During

reads, a master device must signal an end of data to

the slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave (NAK).

In this case, the slave (MCP3021) will release the bus

to allow the master device to generate the STOP con-

dition.

The MCP3021 supports a bidirectional 2-wire bus and

data transmission protocol. The device that sends data

onto the bus is the transmitter and the device receiving

data is the receiver. The bus has to be controlled by a

master device that generates the serial clock (SCL),

controls the bus access and generates the START and

STOP conditions, while the MCP3021 works as a slave

device. Both master and slave devices can operate as

either transmitter or receiver, but the master device

determines which mode is activated.

FIGURE 5-1:

Data Transfer Sequence on the Serial Bus.

SCL

SDA

(A)

(B)

(D)

(A)

(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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