MCP6021 datasheet(15/34 Pages) MICROCHIP

15 / 34 page

DS21685C-page 15

MCP6021/1R/2/3/4

To use the internal mid-supply reference for an

inverting gain circuit, connect the VREF pin to the

non-inverting input, as shown in Figure 4-8. The

capacitor CB helps reduce power supply noise on the

output.

FIGURE 4-8:

Inverting gain circuit using

VREF (MCP6021 and MCP6023 only).

If you don’t need the mid-supply reference, leave the

VREF pin open.

4.7

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good, high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with nearby analog parts.

4.8

Unused Op Amps

An unused op amp in a quad package (MCP6024)

should be configured as shown in Figure 4-9. These

circuits prevent the output from toggling and causing

crosstalk. Circuit A can use any reference voltage

between the supplies, provides a buffered DC voltage,

and minimizes the supply current draw of the unused

op amp. Circuit B uses the minimum number of compo-

nents and operates as a comparator; it may draw more

current.

FIGURE 4-9:

Unused Op Amps.

4.9

PCB Surface Leakage

In applications where low input bias current is critical,

PCB (printed circuit board) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6021/1R/2/3/4 family’s bias current at +25°C

(1 pA, typ).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

Figure 4-10 shows an example of this type of layout.

FIGURE 4-10:

Example Guard Ring

Layout.

Non-inverting Gain and Unity-Gain Buffer.

Connect the guard ring to the inverting input

pin (VIN–); this biases the guard ring to the

common mode input voltage.

Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

Inverting (Figure 4-10) and Transimpedance

Gain Amplifiers (convert current to voltage, such

as photo detectors).

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp’s input (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

4.10

High Speed PCB Layout

Due to their speed capabilities, a little extra care in the

PCB (Printed Circuit Board) layout can make a

significant difference in the performance of these op

amps. Good PC board layout techniques will help you

achieve the performance shown in Section 1.0 “Elec-

trical Characteristics” and Section 2.0 “Typical Per-

formance Curves”, while also helping you minimize

EMC (Electro-Magnetic Compatibility) issues.

Use a solid ground plane and connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

VIN

VOUT

VREF

VDD

¼ MCP6144 (A)

¼ MCP6144 (B)

VDD

Guard Ring

VIN–VIN+

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