© 2005 Microchip Technology Inc.

DS21481C-page 5

TC911A/TC911B

3.3

Avoiding Latchup

Junction isolated CMOS circuits inherently contain a

parasitic p-n-p-n transistor circuit. Voltages exceeding

the supplies by 0.3V should not be applied to the

device pins. Larger voltages can turn the p-n-p-n

device on, causing excessive device power supply cur-

rent and excessive power dissipation. TC911 power

supplies should be established at the same time or

before input signals are applied. If this is not possible,

input current should be limited to 0.1mA to avoid trig-

gering the p-n-p-n structure.

3.4

Overload Recovery

The TC911 recovers quickly from the output saturation.

Typical recovery time from positive output saturation is

20msec. Negative output saturation recovery time is

typically 5msec.