M66239FP datasheet(19/24 Pages) RENESAS

номер детали	M66239FP

подробное описание детали	High Speed Standard Clock Generator With Frequency Synthesizer

PDF	24 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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19 / 24 page

M66239FP

Rev.1.00 Mar 16, 2005 page 19 of 23

Timing Requirements

(Ta = 0 to +50°C, Vcc = 3.15 to 3.46V, GND = 0V)

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

MCLK frequency

fMCLK

—

100

MHz

MCLK and SCLK clock duty

fDUTY

—

TR input pulse width

tw(TR)

500

—

MCLK and SCLK input rising time

—

MCLK and SCLK input falling time

—

SDATA, SENABLE set-up time

tDS

—

SDATA, SENABLE hold time

tDH

—

SCLK frequency

fSCLK

—

MHz

Internal PLL lock up time

Tplllock

—

RESET pulse width

tw(RESET)

—

µs

CL = 10 pF

Switching Characteristics

(Ta = 0 to +50°C, Vcc = 3.15 to 3.46V, GND = 0V)

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Synchronizing precision (jitter)

∆t

—

±1.5

Sync. clock CKO output start time

tss(CKO)

Sync. clock CKOB output start time

tss(CKOB)

—

tLp+50

One-shot pulse output start time

tss(PULSE)

—

tLp+50

Sync clock CKO output stop time

tsp(CKO)

Sync. clock CKOB output stop time

tsp(CKOB)

—

One-shot pulse width

tw(PULSE)

2 tp–10

—

2 tp+10

Sync. clock CKO output duty

foDUTY(CKO)

Sync. clock CKOB output duty

foDUTY(CKOB)

—

CL = 10 pF

Notes: 1. tp = 1/fIN, tLp = tp

× (100 – fDUTY)/100

2. Switching test waveform

Input pulse level MCLK: 0 to Vcc, TR: 0 to Vcc

Input clock rising time: 3 ns

Input clock falling time: 3 ns

Criteria Voltage MCLK: Vcc/2, TR: 1.3 V, Sync. clock: Vcc/2

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