SPSB100 datasheet(40/214 Pages) STMICROELECTRONICS

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It is possible to disable the watchdog in ACTIVE - LOW-POWER mode only through the WD_LP_ENA bit set at

“0” (only after SPI_PROTECT_ACCESS has been set). If WD_LP_ENA is set high during ACTIVE - LOW-

POWER mode, the watchdog will stay disabled and will restart with a long open window after the transition Active-

LP to Active-FP.

Fault conditions can be detected through the following bits:

•

The status bit WD_ENA_ECHO indicates that the watchdog is running when high.

•

The status bit WD_ENA_ECHO_ERROR indicates a watchdog echo error and generates an IRQ. This

error can be masked by MASK_WD_ENA_ECHO_ERROR_IRQ.

•

In case of watchdog fail a flag WDFAIL is set and the watchdog fail counter WDFAIL_CNT is incremented

up to 15 consecutive watchdog trig faults. After 15 consecutive watchdog trig faults, the bit

FORCED_SLEEP_WDFAIL is set and the device will reach the DEEP-SLEEP state.

•

WDFAIL_CNT can be reset by CLR_WDFAIL_CNT bit.

•

The microcontroller can know the current state of watchdog by reading WD_TIMER_STATE(1-0)

WD_TIMER_STATE = 00, WD trig is too early widow trig, WD_TIMER_STATE = 01, WD trig is in valid

window trig.

3.11

FIN1 input

SPSB100 integrates an MCU fault monitoring called FCCU. FCCU block can be configured to detect error

reported by the MCU through FIN1 input. Two error reporting protocols are available: static and dynamic

protocols.

3.11.1

Static protocol

In this protocol MCU signals its own errors to SPSB100 by driving FIN1 input pin at low or high level.

MCU shall configure the SPSB100 FCCU block as the following:

•

FCCU_PROTOCOL shall be reset to 0.

•

FCCU_STATIC_ERROR shall be reset to 0 if MCU signals error driving FIN1 low, or set to 1 if MCU signals

error driving FIN1 high.

•

MCU shall drive FIN1.

•

FCCU_ENA shall be set at 1 to enable the monitoring feature (only after SPI_PROTECT_ACCESS has

been set).

3.11.2

Dynamic protocol

In this protocol MCU signals its own error to SPSB100 by increasing the period, or half period, of the toggling

signal sent to FIN1 input.

The FCCU block shall be programmed to monitor half period of the toggling signal received on FIN1. The FCCU

block is made of a counter clocked by a 400 kHz clock derived from the main oscillator. The counter is reset at

each transition on FIN1 input, if the counter overflows then an error is signaled.

The counter overflow threshold is programmed on FCCU_COUNTER<12:0> (only after SPI_PROTECT_ACCESS

has been set). The oscillator accuracy shall be considered to calculate the value of this threshold, the following

formula can be used:

FCCU_COUNTER > FIN1_half_period * (400 kHz + main oscillator accuracy)

Example: with an MCU toggling signal at 4 882.8 Hz (min) with 50% of duty cycle, and 20% accuracy of SPSB100

oscillator.

FCCU_COUNTER > (204.8/2) µs * (400 kHz * 1.2) = 49.15

Gives FCCU_COUNTER = 50 at minimum.

MCU shall configure the SPSB100 FCCU block as the following:

•

FCCU_PROTOCOL shall be set to 1.

•

FCCU_STATIC_ERROR can be used to configure an internal pull-up (set to 1) or an internal pull-down

(reset to 0) on FIN1 input.

•

FCCU_COUNTER shall be loaded to the overflow threshold (only after SPI_PROTECT_ACCESS has

been set).

•

MCU shall drive FIN1 with the proper toggling signal.

•

FCCU_ENA shall be set at 1 to enable the monitoring feature (only after SPI_PROTECT_ACCESS has

been set).

SPSB100

Functional description

DS14640 - Rev 1

page 40/214

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