A Product Line of

Diodes Incorporated

PI6CB332000

11

June 2024

© 2024 Copyright Diodes Incorporated. All Rights Reserved.

PI6CB332000

Document Number DS41283 Rev 7-2

www.diodes.com

Symbol

Parameters

Condition

Min. Typ. Max.

Spec

Limit

Units

tjPHASE

Additive Integrated Phase

Jitter (RMS)(1,2,7,8)

PCIe Gen 1(6)

—

0

0.03

86

ps

(pkpk)

PCIe Gen 2 Low Band, 10kHz < f

< 1.5MHz (PLL BW 5-16MHz or

8-5MHz, CDR = 10MHz)

—

0

0.03

3

ps

PCIe Gen 2 High Band, 1.5MHz

< f < Nyquist (50MHz); (PLL BW

5-16MHz or 8-5MHz, CDR =

10MHz)

—

0

0.03

3.1

ps

PCIe Gen 3 (PLL BW 2-4MHz or

2-5MHz, CDR = 10MHz)

—

0

0.03

1

ps

PCIe Gen 4 (PLL BW 2-4MHz or

2-5MHz, CDR = 10MHz)

—

0

0.03

0.5

ps

PCIe Gen 5 (PLL BW of 500K to

1.8MHz, CDR = 20MHz) (9)

—

0.015

0.03

0.15

ps

PCIe Gen 6 (PLL BW 500K to

1MHz, CDR = 10MHz)

—

0.008

0.016

0.1

ps

100MHz (12kHz to 20MHz),

input jitter ~156fs

—

87

120

NA(10)

fs

156.25MHz (12kHz to 20MHz),

input jitter ~110fs

—

47

100

NA(10)

fs

100MHz, apply DB2000Q filter,

see figure 5

—

—

25

80

fs

Note:

1. Guaranteed by design and characterization—not 100% tested in production.

2. Measured from differential waveform.

3. Slew rate is measured through the Vswing voltage range centered around differential 0V within ±150mV window.

4. Slew rate matching is measured through ±75mV window centered around differential zero.

5. See http://www.pcisig.com for complete specifications.

6. Sample size of at least 100k cycles. This can be extrapolated to 108ps pk-pk @ 1M cycles for a BER of 10-12.

7. Applies to all differential outputs.

8. For additive jitter RMS value is calculated by the following equation = SQRT [(total jitter)*2 - (input jitter)*2].

9. PCIe Gen 5 v0.9 specification

10. Not available.

PCIe Common Clock (CC) Architecture Jitter