 2004 Microchip Technology Inc.

DS21226E-page 3

24LCS61/24LCS62

TABLE 1-2:

AC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING DATA

All parameters apply across the specified

operating ranges unless otherwise noted.

Vcc = +2.5V to 5.5V

Parameter

Symbol

STD MODE

Vcc = 4.5V - 5.5V

FAST MODE

Units

Remarks

Min.

Max.

Min.

Max.

Clock frequency

—

100

—

400

kHz

Clock high time

4000

—

600

—

ns

Clock low time

4700

—

1300

—

ns

SDA and SCL rise time

—

1000

—

300

ns

SDA and SCL fall time

—

300

—

300

ns

Start condition hold time

4000

—

600

—

ns

After this period the first

clock pulse is generated

Start condition setup time

4700

—

600

—

ns

Only relevant for repeated

Start condition

Data input hold time

0—

0

—

ns

(Note 2)

Data input setup time

250

—

100

—

ns

Stop condition setup time

4000

—

600

—

ns

Output valid from clock

—

3500

—

900

ns

(Note 2)

Bus free time

4700

—

1300

—

ns

Time the bus must be free

before a new transmission

can start

Output fall time

—

250

20 +0.1

250

ns

Input filter spike suppression

(SDA and SCL pins)

—

50

—

50

ns

(Notes 1, 3)

Write cycle time

—

10

—

10

ms

Byte or Page mode

Endurance

1M

—

1M

—

mode (Note 4)

Note 1:

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3:

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site.

SCL

SDA

IN

Tsu:sta

SDA

OUT