24C01SC/24C02SC

DS21170E-page 8

 2004 Microchip Technology Inc.

6.4

Noise Protection

circuit which disables the internal erase/write logic if the

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

FIGURE 6-1:

CURRENT ADDRESS READ

FIGURE 6-2:

RANDOM READ

FIGURE 6-3:

SEQUENTIAL READ

SP

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

Control

Byte

Data n

A

C

K

N

O

A

C

K

S

T

O

P

S

P

S

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

Control

Byte

Word

Address (n)

Data n

A

C

K

A

C

K

N

O

A

C

K

Control

Byte

A

C

K

S

T

A

R

T

P

SDA LINE

BUS ACTIVITY

S

T

O

P

Control

Byte

Data n

A

C

K

N

O

A

C

K

A

C

K

A

C

K

A

C

K

Data n + 1

Data n + 2

Data n + X

BUS ACTIVITY

MASTER