24LC41A-SLASHP datasheet(12/18 Pages) MICROCHIP

12 / 18 page

24LC41A

DS21176D-page 12

 2003 Microchip Technology Inc.

6.0

WRITE PROTECTION

6.1

DDC Monitor Port

When using the DDC Monitor Port in the Bidirectional

mode, the VCLK pin operates as the write-protect

control pin. Setting VCLK high allows normal write

operations, while setting VCLK low prevents writing to

any location in the array. Connecting the VCLK pin to

VSS would allow the monitor port to operate as a serial

ROM, although this configuration would prevent using

the device in the Transmit-only mode.

7.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read

and sequential read. These operations are identical for

both the DDC Monitor Port (in Bidirectional mode) and

the Microcontroller Access Port and are completely

independent of one another.

7.1

Current Address Read

The port contains an address counter that maintains

the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address n, the

next current address read operation would access data

from address n + 1. Upon receipt of the slave address

with R/W bit set to one, the port issues an acknowledge

and transmits the 8-bit data word. The master will not

acknowledge the transfer but does generate a Stop

condition and the port discontinues transmission

(Figure 7-1).

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

port as part of a write operation. After the word address

is sent, the master generates a Start condition following

the acknowledge. This terminates the write operation,

but not before the internal address pointer is set. The

master then issues the control byte again, but with

the R/W bit set to a one. The port then issues an

acknowledge and transmits the 8-bit data word. The

master will not acknowledge the transfer but does

generate a Stop condition and the port discontinues

transmission (see Figure 7-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the port transmits the

first data byte, and the master issues an acknowledge

as opposed to a Stop condition in a random read. This

directs the port to transmit the next sequentially

addressed 8-bit word (see Figure 7-3).

To provide sequential reads, the port contains an

internal address pointer, which is incremented by one

at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

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