24FC32-SLASHP datasheet(8/16 Pages) MICROCHIP

8 / 16 page

24FC32

DS21126E-page 8

 2004 Microchip Technology Inc.

6.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

6.1

Current Address Read

The 24FC32 contains an address counter that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address n (n is any legal address), the next current

address read operation would access data from

address n + 1. Upon receipt of the slave address with

R/W bit set to one, the 24FC32 issues an acknowledge

and transmits the eight bit data word. The master will

not acknowledge the transfer but does generate a Stop

condition and the 24FC32 discontinues transmission

(Figure 6-1).

6.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24FC32 as part of a write operation (R/W bit set to 0).

After the word address is sent, the master generates a

Start

condition

following

the

acknowledge.

This

terminates the write operation, but not before the

internal address pointer is set. Then the master issues

the control byte again but with the R/W bit set to a one.

The 24FC32 will then issue an acknowledge and

transmit the eight bit data word. The master will not

acknowledge the transfer but does generate a Stop

condition which causes the 24FC32 to discontinue

transmission (Figure 6-2).

FIGURE 6-1:

CURRENT ADDRESS READ

6.3

Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 256K

bits by adding up to eight 24FC32's on the same bus.

In this case, software can use A0 of the control byte as

address bit A12, A1 as address bit A13, and A2 as

address bit A14.

6.4

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24FC32 transmits

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24FC32 to transmit

the next sequentially addressed 8 bit word (Figure 6-3).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge but will

generate a Stop condition.

To provide sequential reads the 24FC32 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation. The address pointer, however,

will not roll over from address 07FF to address 0000. It

will roll from 07FF to unused memory space.

6.5

Noise Protection

The SCL and SDA inputs incorporate Schmitt Triggers

which suppress noise spikes to ensure proper device

operation even on a noisy bus.

CONTROL

BYTE

DATA n

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

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