MPR081 datasheet(15/22 Pages) FREESCALE

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MPR081

Sensors

Freescale Semiconductor

Table 19. Configuration Register Format

R/W

Address

Read Configuration Register

0x09

Interrupt Rate

RESET N/A WAKE IRQEN

RUN

Write Configuration Register

MPR081 is in shutdown, and will not scan the rotary.

Note that FIFO contents are not cleared when entering shutdown

and can be read any time during shutdown.

MPR081 is operating, scanning the rotary, with IRQ interrupt

output disabled. Poll the FIFO register 0x00 and/or the Current

Rotary register 0x02 to determine current rotary status.

Note that FIFO contents are cleared before exiting shutdown

MPR081 is operating, scanning the rotary, with IRQ interrupt

output enabled. IRQ behavior is controlled by Interrupt Rate bits

D5-D7, and is asserted on the first entry into the FIFO from

empty.

Note that FIFO contents are cleared before exiting shutdown

MPR081 will go into low power sleep mode after an idle period

timeout. While in low power sleep mode, device cannot be

addressed via I2C except by asserting the wake pin.

MPR081 will remain awake and can be addressed at anytime via

I2C.

System reset asserted. MPR081 can be addressed via I2C at

anytime.

System reset de-asserted. MPR081 can be addressed via I2C at

anytime.

IRQ interrupt is immediate when FIFO changes from empty

IRQ interrupt asserts no sooner than 4 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 12 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 20 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 28 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 36 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 44 master tick periods after

the last IRQ rise

IRQ interrupt asserts no sooner than 52 master tick periods after

the last IRQ rise

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