| поискавой системы для электроныых деталей |
|
LTC6902 датащи(PDF) 11 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
LTC6902 датащи(HTML) 11 Page - Analog Devices |
|
11 / 16 page ![]() LTC6908-1/LTC6908-2 11 Rev C For more information www.analog.com RSET (Ω) 100 1000 1k 100k 1M 10M 690812 F07 10 10k 10000 TA = 25°C V+ = 3V the bandwidth of the switching regulator is sufficient, not a difficult requirement in most cases, the regulator’s regulation, efficiency and load response are maintained while peak electromagnetic radiation (or conduction) is reduced. Output ripple may be somewhat increased, but its behavior is very much like noise and its system impact is benign. HIGH FREQUENCY REJECTION Using the LTC6908 in spread spectrum mode naturally eliminates any concerns for output frequency accuracy and stability as it is continually hopping to new settings. In fixed frequency applications however, some attention to V+ supply voltage ripple is required to minimize additional output frequency error. Ripple frequency components on the supply line near the programmed output frequency of the LTC6908 in excess of 30mVP-P could create an additional 0.2% of frequency error. In applications where a fixed frequency LTC6908 output clock is used to syn- chronize the same switching regulator that provides the V+ supply to the oscillator, noticeable jitter of the clock may occur if the ripple exceeds 30mVP-P . START-UP TIME The start-up time and settling time to within 1% of the final value can be estimated by tSTART ≈ RSET • (2.5µs/k) + 10µs. For instance, with RSET = 100k, the LTC6908 will settle to within 1% of its 1MHz final value in approxi- mately 260µs. Figure 7 shows start-up times for various RSET resistors. An internal counter mutes the outputs (OUT1 = Low, OUT2 = High) for the first 64 clock cycles after power-up, ensuring that the first clock cycle is close to the desired operating frequency. JITTER The Peak-to-Peak Jitter vs Output Frequency graph, in the Typical Performance Characteristics section, shows the typical clock jitter as a function of oscillator frequency and power supply voltage. These specifications assume that the capacitance on SET is limited to less than 10pF, as suggested in the Pin Functions description. If this require- ment is not met, the jitter will increase. Figure 7. Start-Up Time APPLICATIONS INFORMATION |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |