1999 Jan 13

7

Philips Semiconductors

Product specification

5 V mixer/oscillator-PLL synthesizers for

hyperband tuners

TDA6404; TDA6405;

TDA6405A

Table 1

Table 2

The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several

synthesizers (up to 4) in one system by applying a specific voltage on the AS input. The relationship between MA1 and

MA0 and the input voltage applied to the AS input is given in Table 4.

Table 3

Description of symbols used in Tables 1 and 2

NAME

BYTE

BITS

ACK

MSB

LSB

Address byte

ADB

11000

MA1

MA0

R/W=0

A

Divider byte 1

DB1

0

N14

N13

N12

N11

N10

N9

N8

A

Divider byte 2

DB2

N7

N6

N5

N4

N3

N2

N1

N0

A

Control byte

CB

1

CHP

T2

T1

T0

RSA

RSB

OS

A

Band-switch byte

BB

XXXXX

UHF

VHFH

VHFL

A

NAME

BYTE

BITS

ACK

MSB

LSB

Address byte

ADB

11000

MA1

MA0

R/W=0

A

Divider byte 1

DB1

0

N14

N13

N12

N11

N10

N9

N8

A

Divider byte 2

DB2

N7

N6

N5

N4

N3

N2

N1

N0

A

Control byte

CB

1

CHP

T2

T1

T0

RSA

RSB

OS

A

Band-switch byte

BB

XXXX

UHF

X

VHFH

VHFL

A

SYMBOL

DESCRIPTION

A

acknowledge

MA1 and MA0

programmable address bits (see Table 4)

N14 to N0

programmable divider bits; N = N14

CHP

charge pump current bit:

T2, T1 and T0

test bits (see Table 5)

RSA and RSB

reference divider ratio select bits (see Table 6)

OS

tuning amplifier control bit:

OS = 0; normal operation; tuning voltage is ‘ON’

OS = 1; tuning voltage is ‘OFF’ (high-impedance)

UHF, VHFH and VHFL

PNP ports control bits:

bit = 0; buffer n is ‘OFF’ (default)

bit = 1; buffer n is ‘ON’

X

don’t care bit: may be a logic 0 or a logic 1