Dual-Channel, 14-Bit, CCD Signal

AD9974

Rev. Sp0

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FEATURES

1.8 V analog and digital core supply voltage

Correlated double sampler (CDS) with

−3 dB, 0 dB, +3 dB, and +6 dB gain

6 dB to 42 dB, 10-bit variable gain amplifier (VGA)

14-bit, 65 MHz analog-to-digital converter (ADC)

Black level clamp with variable level control

Complete on-chip timing generator

Precision Timing core with 240 ps resolution @ 65 MHz

On-chip 3 V horizontal and RG drivers

100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package

Internal LDO regulator circuitry

APPLICATIONS

Professional HDTV camcorders

Professional/high end digital cameras

Broadcast cameras

Industrial high speed cameras

GENERAL DESCRIPTION

The AD9974 is a highly integrated, dual-channel CCD signal

processor for high speed digital video camera applications. Each

channel is specified at pixel rates of up to 65 MHz. The AD9974

consists of a complete analog front end with analog-to-digital

conversion combined with a programmable timing driver. The

Precision Timing core allows adjustment of high speed clocks

with approximately 240 ps resolution at 65 MHz operation.

Each analog front end includes black level clamping, CDS, VGA,

and a 65 MSPS, 14-bit ADC. The timing driver provides the high

speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,

and H1_B to H4_B outputs. A 3-wire serial interface is used to

program each channel of the AD9974.

Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,

the AD9974 is specified over an operating temperature range of

−25°C to +85°C.

For more information on the AD9974, email Analog Devices, Inc. at

afe.ccd@analog.com.

FUNCTIONAL BLOCK DIAGRAM

AD9974

SYNC

GENERATOR

PRECISION

TIMING

CORE

INTERNAL CLOCKS

HORIZONTAL

DRIVERS

RG_B

RG_A

H1_A TO H4_A

4

H1_B TO H4_B

4

HD_A VD_A HD_B VD_B

INTERNAL

REGISTERS

SL_A

SDATA_A

SL_B

SDATA_B

SCK_A

SCK_B

CLI_A

CLI_B

CLAMP

DOUT_A

CCDINP_A

6dB TO 42dB

VGA

ADC

CDS

14

CLAMP

DOUT_B

CCDINP_B

6dB TO 42dB

VGA

ADC

CDS

14

REFT_B REFB_B

VREF_B

REFT_A REFB_A

VREF_A

–3, 0, +3, +6dB

–3, 0, +3, +6dB

1.8V OUTPUT

LDO A

1.8V OUTPUT

LDO B

CCDINM_A

CCDINM_B

Figure 1.