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Rev. A 04/07

Power Integrations

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protects Q2 from short circuit conditions by limiting the collector

current, while R5 maintains regulation even if the -5 V output is

unloaded. Locating transistors Q1 and Q2 physically close to

one another provides tracking of V

voltage variation with temperature.

This arrangement works well in this application, where the

load range is limited and the impact on efficiency of linear

regulation is minimized.

Key Design Points

• Diode D2 must be an ultra-fast type. The MURS160

selected has a t

(≤50 ns) may be used, but efficiency may be reduced.

• A Zener with a low test current should be selected for

VR1. The initial tolerance directly affects the output

tolerance, a 2% part gives an overall variation including

line and load regulation of ±5%.

• The temperature coefficient of VR1 is –0.8 mV/°C, giving

a further ±0.4% variation over a temperature of 0 to 50 °C.

• R1 and R2 should be 1% parts for better accuracy of 12 V

output.

• Pre-loads R5 and R6 are only necessary if regulation at

no-load is required.

• For single 230 VAC applications, the value of C1 and C2

can be reduced to 2.2 μF, depending on differential surge

Figure 2. Worst Case Load and Line Regulation Results.

Figure 3. Conducted EMI Scan to EN55022B Limits Measured at

230 VAC Input.

and EMI requirements. For single 100/115 VAC

applications, the voltage of C1 and C2 can be reduced

to 200 V.

• For correct operation of Q1, select the value of R5 to

give 1 mA at no-load.

• Limit the maximum value of R4 such that a minimum

V

Q2 remains in linear operation when the 5 V output is

at full load.

0

20

40

80

60

100

% Full Load

4

3

2

0

1

-3

-2

-1

-4

7 V output at 265 VAC (5 V at min load)

-5 V output at 265 VAC (12 V at no load)

7 V output at 185 VAC (5 V at full load)

-5 V output at 185 VAC (12 V at full load)

1.0

0.15

10.0

100.0

-20

-10

0

10

20

30

40

50

60

80

70

MHz

QP

AV