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DI-117 датащи(PDF) 2 Page - Power Integrations, Inc. |
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DI-117 датащи(HTML) 2 Page - Power Integrations, Inc. |
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2 / 2 page ![]() Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. The products and applications illustrated herein (transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations' patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2006, Power Integrations, Inc. For the latest updates, visit www.powerint.com DI-89 DI-117 Rev. A 09/06 Power Integrations 5245 Hellyer Avenue San Jose, CA 95138 Phone: 1-408-414-9200 Apps: 1-408-414-9660 Apps Fax: 1-408-414-9760 For a complete listing of worldwide sales offices, please visit www.powerint.com The built-in frequency jitter and E-ShieldTM techniques allow simple EMI filtering to comply with EN55022B. Resistor R2 and C4 form an RC snubber to reduce high-frequency EMI. Outputovervoltageprotection(OVP)isprovidedontheprimary sidebysensingthevoltageoftheauxiliarytransformerwinding. Shouldthemainfeedbackloopopen duetofailureofU2,thenU1 willlatchoffoncethecurrentintotheBP/Mpin(viaVR3)exceeds 6.5 mA. Diode D6 and capacitor C7 rectify and smooth the output of the auxiliary winding. The value of VR3 is selected to trigger the OVP latch when the main output, and hence the auxiliaryoutputvoltage,risesabovethenormalregulationrange. Once triggered, cycling the AC power resets the OVP latch. To reduce no-load input power and thus increase light load efficiency, resistor R3 feeds the supply current for U1 from the auxiliary winding on the transformer. Key Design Points • Verify maximum drain voltage is <650 V at high line, maximum overload. Adjust values of R5, R6 and C5 accordingly. However, avoid making the clamp too dissipative (low value of R5 and R6, and high value of C5) as this will increase no-load consumption. • To prevent an increase in no-load consumption or false OVP triggering, VR3 should be selected to conduct only when the output voltage is outside the normal regulationrange.ResistorR4preventsexcessivecurrent from flowing into the BP/M pin. • Fast recovery glass-passivated diodes were selected for D1 and D3 to reduce low frequency conducted EMI. Fast diodes such as FR107 are also suitable. Figure 2. Worst-Case Open Loop Output Overvoltage (85 VAC, Full Load). 0 50 100 5 20 15 25 10 Time (ms) 30 35 0 -5 Table 1. Transformer Design Parameters. T.I.W.: Triple Insulated Wire, NC: No Connection TRANSFORMER PARAMETERS Core Material EF20, N67 or equivalent, gap for A LG of 203 nH/T 2 Bobbin 5+5 pin horizontal Winding Details Shield: 24T, 28 AWG Primary: 62T, 31 AWG Bias: 5T, 4 × 28 AWG 12 V: 7T, 23 AWG T.I.W. Winding Order (Pin Numbers) 3 mm tape margin, shield (1-NC), tape, primary (3-1), tape, bias (5-4), tape, 12 V (10-9), tape Inductance Primary: 790 µH ±7% Leakage: 30 µH (max) Primary Resonant Frequency 650 kHz (min) |
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