Power Integrations reserves the right to make changes to its products at any time to improve reliability or

manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit

described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL

WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS

FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. The products and applications

illustrated herein (transformer construction and circuits external to the products) may be covered by one or more U.S.

and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A

complete list of Power Integrations' patents may be found at

www.powerint.com. Power Integrations grants its

customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.

The PI logo,

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Clampless, E-Shield, Filterfuse, PI Expert and PI FACTS are trademarks of Power Integrations, Inc.

Other trademarks are property of their respective companies. ©Copyright 2006, Power Integrations, Inc.

For the latest updates, visit

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Rev. A 09/06

Power Integrations

5245 Hellyer Avenue

San Jose, CA 95138

Phone: 1-408-414-9200

Apps: 1-408-414-9660

Apps Fax: 1-408-414-9760

For a complete listing of worldwide

sales offices, please visit

www.powerint.com

Table 1. Transformer Design Parameters.

Figure 2. Worst-Case Conducted EMI Results

(Output Connected to Safety Earth ground).

Key Design Points

• The primary clamp of D5, R1, VR3, R2 and C3 is an

optimized RCD clamp. During full load, VR3 limits the

maximum voltage across C3. At light-load or no-load, as

the effective switching frequency is reduced, VR3 prevents

C3 from discharging completely. This prevents the clamp

network from appearing as a significant load. The use of

a fast vs. ultra-fast diode for D5 improves efficiency by

recycling some of the leakage energy to the output.

• Select the value of VR1 and VR2 to limit the maximum

voltageduringanopenloopfault. ResistorR13provides

a bias current so that the Zeners are operated closer to

their test current. This bias current also acts as a pre-

load.

• For improved cross-regulation, feedback for the power

supply is provided from both the 5 V and 12 V output

into the voltage reference U4 via R14 and R15.

TRANSFORMER PARAMETERS

Core Material

EE25, N67 or equivalent, gap

for A

2

Bobbin

5+5 pin vertical (Yih-Hwa YW-

360-02B)

Winding Details

Bias: 27T, 29 AWG

Primary: 105T, 32 AWG

Shield: 2T, 100 mm

× 9 mm ×

1 mil Cu foil

+5 V: 5T, 2

×

24 AWG T.I.W.

+12 V: 6T, 25 AWG T.I.W.

-12 V: 11T, 32 AWG T.I.W.

-24 V: 11 T, 32 AWG T.I.W.

Winding Order

(pin numbers)

1 mm tape margin, bias (4-

5), tape, primary (3-2), shield

(2-NC), tape, +5 V (6-7), +12 V

(8-6), tape, -12 V (7-10), -24 V

(10-9), tape

Inductance

Primary: 1.15 mH - 0/+10%

Leakage: 70

µH (max)

1.0

EN55022B Limits

0.15

10.0

100.0

-20

-10

0

10

20

30

40

50

60

80

70

MHz

QP

AV