AD3552R datasheet(2/66 Pages) AD

2 / 66 page

Data Sheet

AD3542R

TABLE OF CONTENTS

analog.com

Rev. C | 2 of 66

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................1

Specifications........................................................ 4

Electrical Characteristics.................................... 4

AC Characteristics..............................................6

Timing Characteristics........................................6

Absolute Maximum Ratings.................................10

Thermal Resistance......................................... 10

ESD Caution.....................................................10

Pin Configuration and Function Descriptions.......11

Typical Performance Characteristics................... 13

Terminology......................................................... 25

Theory of Operation.............................................27

Product Description.......................................... 27

DAC Architecture..............................................27

Output Voltage Spans...................................... 27

Transfer Function............................................. 27

Internal TIA.......................................................27

TIA Power Consumption.................................. 27

VREF..................................................................28

SPI Register Map Access.................................28

Serial Interface................................................. 34

DAC Update Modes......................................... 37

Power-Down.....................................................38

Reset................................................................38

Error Detection................................................. 38

ALERT Pin........................................................40

Device ID..........................................................41

Summary of Interface Access Modes...............41

Registers............................................................. 42

Interface Register Details................................. 45

DAC Register Details....................................... 54

Applications Information...................................... 65

Power Supply Recommendations.................... 65

Layout Guidelines.............................................65

Outline Dimensions............................................. 66

Ordering Guide.................................................66

Evaluation Boards............................................ 66

REVISION HISTORY

7/2023—Rev. B to Rev. C

Changed VINH to VIH and VINL to VIL (Throughout).......................................................................................... 1

Changes to Figure 1........................................................................................................................................ 1

Changes to Table 3..........................................................................................................................................6

Changes to Output Range Register Section and Table 38............................................................................ 57

Changes to Power Supply Recommendations Section................................................................................. 65

4/2023—Rev. A to Rev. B

Changes to General Description Section.........................................................................................................1

Change to Table 5..........................................................................................................................................10

Changes to Figure 10 and Table 7................................................................................................................. 11

Changes to Relative Accuracy or Integral Nonlinearity (INL) Section............................................................25

Changes to Differential Nonlinearity (DNL) Section.......................................................................................25

Changes to DC PSRR and AC PSRR Section.............................................................................................. 25

Changes to Output Voltage Settling Time Section.........................................................................................25

Changes to Digital-to-Analog Glitch Impulse Section.................................................................................... 25

Changes to Digital Feedthrough Section....................................................................................................... 25

Changes to Output Noise Spectral Density Section...................................................................................... 25

Changes to Total Harmonic Distortion (THD) Section....................................................................................25

Changes to DC Crosstalk Section................................................................................................................. 26

Changes to DAC Architecture Section and Figure 79....................................................................................27

Changes to Output Voltage Spans Section and Table 8................................................................................ 27

Changes to TIA Power Consumption Section................................................................................................27

Change to Figure 84...................................................................................................................................... 29

Changes to Streaming Mode Section ........................................................................................................... 30

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